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dc.contributor.advisor Ismail, Yehea
dc.contributor.advisor Helmy, Amr
dc.contributor.author Haridy, Omar Fathy
dc.creator Haridy, Omar Fathy
dc.date.accessioned 2012-07-17T22:38:36Z
dc.date.available 2013-01-14T04:00:08Z
dc.date.created 2012 Summer
dc.date.issued 2012-07-17T22:38:36Z
dc.identifier.uri http://dar.aucegypt.edu/handle/10526/3196
dc.description.abstract Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies. en
dc.format.medium theses en
dc.language.iso en en
dc.rights Author retains all rights with regard to copyright. en
dc.subject Digital control en
dc.subject Delay Locked Loops (DLL) en
dc.subject Pulse Width Modulator (PWM) signal en
dc.subject Very Large Scale Integrated (VLSI) circuits en
dc.subject Voltage Regulators (VRs) en
dc.subject Register-Transfer Level (RTL) design en
dc.subject Calibration en
dc.subject Process, Voltage, Temperature (PVT) variations en
dc.subject.lcsh Thesis (M.S.)--American University in Cairo en
dc.title Synthesizable delay line architectures for digitally controlled voltage regulators en
dc.type Text en
dc.subject.discipline Electronics Engineering en
dc.rights.access This item is restricted for 6 months from the date issued en
dc.contributor.department American University in Cairo. Dept. of Electronics Engineering en
dc.description.irb American University in Cairo Institutional Review Board approval is not necessary for this item, since the research is not concerned with living human beings or bodily tissue samples. en


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  • Theses and Dissertations [715]
    This collection includes theses and dissertations authored by American University in Cairo graduate students.

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