Modelling the phase step response of digital bang-bang PLLs

Abstract

Bang-Bang Phase Locked Loops (BB-PLLs) are a class of phase locked loops that incorporate binary phase detectors. BB-PLLs offer a low power implementation of PLLs at the cost of nonlinear loop dynamics. Since low power design is currently one of the most significant research areas in the field of VLSI, BB-PLLs have recently gained an increasing interest in the VLSI research communities. Moreover, BB-PLLs can be easily implemented using digital circuits, and thus, enable seamless scaling across technology nodes. The nonlinearity of the BB-PLLs, however, results in a number of problems associated with the design of BB-PLLs. One of the main problems of BB-PLLs is the difficulty in modeling the nonlinear system, which leads to the lack of a well-defined design methodology. Another problem of BB-PLLs is that the response of the system depends on the Phase Error Magnitude (PEM), and thus, the system does not have a constant Bandwidth (BW). These problems make the BB-PLLs undesirable for many applications. The main focus of this work is to develop a generic modeling methodology that can be applied to any Digital BB-PLL to predict the response of the BB-PLL prior to starting the circuit design. The benefit of this modeling methodology is to define a design methodology for BB-PLLs, and to facilitate the design process. In order to verify the proposed model, a conventional Digital BB-PLL is implemented on the circuit level, and compared to the model. Moreover, the insights gained by the model are used to propose techniques that can be used to enhance the system linearity. Verified by AMS simulations, the model is proved to be successful in predicting the system response. Furthermore, the proposed techniques are compared to the conventional system. Simulations demonstrated that the impact of the proposed techniques is about 35% enhancement in the system linearity, and 55% reduction in the settling time of the phase step response.