Show simple item record

dc.contributor.advisor Balasa, Florin
dc.contributor.author Abuaesh, Noha
dc.date.accessioned 2014-01-15T12:35:51Z
dc.date.available 2014-01-15T16:00:04Z
dc.date.created 2013 Fall en
dc.date.issued 2014-01-15
dc.identifier.uri http://dar.aucegypt.edu/handle/10526/3779
dc.description.abstract In real-time data-intensive multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space – namely power consumption, performance, and chip area. Hierarchical memory organizations are used in embedded systems to reduce energy consumption and improve performance by exploiting the non-uniformity of memory accesses, by assigning the frequently-accessed data to low levels of the hierarchy. Moreover, within a given level, energy can be further reduced and performance further enhanced by memory partitioning – whose principle is to divide the address space in several smaller blocks and to map these blocks to physical memory banks. Scratch-pad memories (SPMs) offer a good compromise – as on-chip storage in embedded systems – when taking into account performance, energy consumption, and die area. This thesis addresses the problem of optimizing the partitioning of SPMs. Different from previous techniques, this approach has as main input the application code, rather than a memory access trace obtained by simulation. The approach builds upon a framework that employs a formal model operating with integral polyhedra, using techniques specific to the data-dependence analysis employed in modern compilers. Thus, and unlike previous techniques, the problems of data assignment to the memory layers and banking the on-chip memory are addressed in a consistent way, based on the same formal model. Another major difference is that the cost function takes into account all the three major design objectives, letting the designers decide on their relative importance for a specific project. The main design target is the reduction of the static and dynamic energy consumption in the memory subsystem, but the same formal model and algorithmic flow can be also applied to reduce the overall time of access to memories. The proposed approach proved to be computationally fast and very efficient when tested for several data-intensive applications, whose behavioral specifications contain multidimensional arrays as main data structures. en
dc.description.sponsorship University research scholarship. en
dc.format.extent 114 p. en
dc.format.medium datasets en
dc.format.medium theses en
dc.language.iso en en
dc.rights Author retains all rights with regard to copyright. en
dc.subject Embedded computer systems en
dc.subject Cacti en
dc.subject Cactus en
dc.subject Memory bank en
dc.subject Digital signal and image processing en
dc.subject CAD/CAM systems en
dc.subject.lcsh Thesis (M.S.)--American University in Cairo en
dc.subject.lcsh Embedded computer systems.
dc.subject.lcsh Cactus.
dc.subject.lcsh Signal processing -- Digital techniques.
dc.title Energy optimization by scratchpad memory banking for embedded systems en
dc.type Dataset en
dc.type Text en
dc.subject.discipline Computer Science en
dc.rights.access This item is available en
dc.contributor.department American University in Cairo. Dept. of Computer Science and Engineering en
dc.description.irb American University in Cairo Institutional Review Board approval is not necessary for this item, since the research is not concerned with living human beings or bodily tissue samples. en
dc.contributor.committeeMember Moustafa, Mohamed
dc.contributor.committeeMember Shalan, Mohamed
dc.contributor.committeeMember Salem, Ashraf


Files in this item

Icon
Icon
Icon

This item appears in the following Collection(s)

  • Theses and Dissertations [1728]
    This collection includes theses and dissertations authored by American University in Cairo graduate students.

Show simple item record