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dc.contributor.advisor Ismail, Yehea
dc.contributor.author Essam, Taher
dc.date.accessioned 2015-01-29T10:48:41Z
dc.date.available 2016-01-29T22:00:11Z
dc.date.created 2015 Winter en_US
dc.date.issued 2015-01-29
dc.identifier.uri http://dar.aucegypt.edu/handle/10526/4269
dc.description.abstract This thesis presents a cell-level framework for Operational Amplifiers Synthesis (OASYN) coupling both circuit design and layout. For circuit design, the tool applies a corner-driven optimization, accounting for on-chip performance variations. By exploring the process, voltage, and temperature variations space, the tool extracts design worst case solution. The tool undergoes sensitivity analysis along with Pareto-optimality to achieve required specifications. For layout phase, OASYN generates a DRC proved automated layout based on a sized circuit-level description. Morata et al. (1996) introduced an elegant representation of block placement called sequence pair for general floorplans (SP). Like TCG and BSG, but unlike O-tree, B*tree, and CBL, SP is P-admissible. Unlike SP, TCG supports incremental update during operation and keeps the information of the boundary modules as well as their relative positions in the representation. Block placement algorithms that are based on SP use heuristic optimization algorithms, e.g., simulated annealing where generation of large number of sequence pairs are required. Therefore a fast algorithm is needed to generate sequence pairs after each solution perturbation. The thesis presents a new simple and efficient O(n) runtime algorithm for fast realization of incremental update for cost evaluation. The algorithm integrates sequence pair and transitive closure graph advantages into TCG-S* a superior topology update scheme which facilitates the search for optimum desired floorplan. Experiments show that TCG-S* is better than existing works in terms of area utilization and convergence speed. Routing-aware placement is implemented in OASYN, handling symmetry constraints, e.g., interdigitization, common centroid, along with congestion elimination and the enhancement of placement routability. en_US
dc.description.sponsorship This research was partially funded by Zewail City of Science and Technology, AUC, the STDF, Intel, Mentor Graphics, ITIDA, SRC and MCIT en_US
dc.format.extent 100 p. en_US
dc.format.medium theses en_US
dc.language.iso en en_US
dc.rights Author retains all rights with regard to copyright. en
dc.subject Analog electronic circuits en_US
dc.subject Synthesis en_US
dc.subject Automation en_US
dc.subject.lcsh Thesis (M.S.)--American University in Cairo en_US
dc.subject.lcsh Operational amplifiers.
dc.subject.lcsh Analog electronic systems.
dc.subject.lcsh Wireless sensor networks.
dc.title A framework for fine-grain synthesis optimization of operational amplifiers en_US
dc.type Still Image en_US
dc.type Text en_US
dc.subject.discipline Electronics Engineering en_US
dc.rights.access This item is restricted for 1 year from the date issued en_US
dc.contributor.department American University in Cairo. Dept. of Electronics Engineering en_US
dc.description.irb American University in Cairo Institutional Review Board approval has been obtained for this item. en_US
dc.contributor.committeeMember Ismail, Yehea
dc.contributor.committeeMember AbouAuf, Ahmed
dc.contributor.committeeMember El-Nozahi, Mohamed


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  • Theses and Dissertations [1863]
    This collection includes theses and dissertations authored by American University in Cairo graduate students.

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