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dc.contributor.advisor Abou-Auf, Ahmed
dc.contributor.author Ibrahim, Mohamed Ayman Ahmed
dc.date.accessioned 2019-09-05T09:54:40Z
dc.date.available 2019-09-05T22:00:07Z
dc.date.created Spring 2019 en_US
dc.date.issued 2019-09-05
dc.identifier.uri http://dar.aucegypt.edu/handle/10526/5779
dc.description.abstract Radiation sources exist in different kinds of environments where electronic devices often operate. Correct device operation is usually affected negatively by radiation. The radiation resultant effect manifests in several forms depending on the operating environment of the device like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL). CMOS circuits and Floating gate MOS circuits suffer from an increase in the delay and the leakage current due to TID effect. This may damage the proper operation of the integrated circuit. Exhaustive testing is needed for devices operating in harsh conditions like space and military applications to ensure correct operations in the worst circumstances. The use of worst case test vectors (WCTVs) for testing is strongly recommended by MIL-STD-883, method 1019, which is the standard describing the procedure for testing electronic devices under radiation. However, the difficulty of generating these test vectors hinders their use in radiation testing. Testing digital circuits in the industry is usually done nowadays using design for testability (DFT) techniques as they are very mature and can be relied on. DFT techniques include, but not limited to, ad-hoc technique, built-in self test (BIST), muxed D scan, clocked scan and enhanced scan. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Despite all these recommendations for DFT, radiation testing has not benefited from this reliable technology yet. Also, with the big variation in the DFT techniques, choosing the right technique is the bottleneck to achieve the best results for TID testing. In this thesis, a comprehensive comparison between different DFT techniques for TID testing of flash-based FPGAs is made to help designers choose the best suitable DFT technique depending on their application. The comparison includes muxed D scan technique, clocked scan technique and enhanced scan technique. The comparison is done using ISCAS’89 benchmarks circuits. Points of comparisons include FPGA resources utilization, difficulty of designs bring-up, added delay by DFT logic and robust testable paths in each technique. en_US
dc.format.extent 107 p. en_US
dc.format.medium theses en_US
dc.language.iso en en_US
dc.rights Author retains all rights with regard to copyright. en
dc.subject TID en_US
dc.subject DFT en_US
dc.subject total ionization dose en_US
dc.subject design for testability en_US
dc.subject FPGA en_US
dc.subject flash-based en_US
dc.subject flash-based FPGA en_US
dc.subject.lcsh Thesis (M.S.)--American University in Cairo en_US
dc.title A comprehensive comparison between design for testability techniques for total dose testing of flash-based FPGAs en_US
dc.type Text en_US
dc.subject.discipline Electronics Engineering en_US
dc.rights.access This item is available en_US
dc.contributor.department American University in Cairo. Dept. of Electronics Engineering en_US
dc.description.irb American University in Cairo Institutional Review Board approval is not necessary for this item, since the research is not concerned with living human beings or bodily tissue samples. en_US
dc.contributor.committeeMember Ismail, Yehea
dc.contributor.committeeMember Wassal, Amr


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  • Theses and Dissertations [1863]
    This collection includes theses and dissertations authored by American University in Cairo graduate students.

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